SHaRe Lab

Research

We develop models, architectures, and hardware systems for neuromorphic computing, intelligent hardware, Physical AI, emerging circuits, and hardware trust.

Our Research Framework

SHaRe connects three levels of research rather than treating algorithms and hardware as separate activities.

1

Models & Algorithms

Neuron models, SNNs, learning, signal processing, event representations, bio-inspired dynamics, and hardware-aware computation.
2

Architectures & Hardware

FPGA, ASIC, RISC-V, embedded, mixed-signal, memristive, and memory-centric architectures.
3

Physical Systems

Event-driven sensing, robotics, biomedical signals, communications, autonomous platforms, and near-sensor intelligence.
Core philosophy: a research idea is most valuable when we understand both its computational behavior and the cost of realizing it in hardware.

1. Neuromorphic Computing

Brain-inspired computation from neuron dynamics to scalable architectures.

Spiking Neural Networks

Architectures, learning, coding, recurrent networks, temporal processing, and hardware-efficient SNN models.

Neuron & Synapse Models

LIF, Izhikevich, AdEx, Hodgkin鈥揌uxley, resonate-and-fire, map-based neurons, nonlinear dynamics, and plastic synapses.

Neuromorphic Architectures

Scalable event-driven compute fabrics, routing, memory organization, heterogeneous accelerators, and distributed systems.

2. Intelligent Hardware

Specialized architectures for efficient AI, signal processing, and domain-specific computation.

FPGA & RTL

Pipelining, parallel datapaths, fixed-point arithmetic, memory hierarchy, high-speed interfaces, verification, and hardware-aware optimization.

ASIC & AI-on-a-Chip

Custom digital architectures, low-power data movement, specialized arithmetic, on-chip memory, accelerator integration, and silicon implementation.

RISC-V & HW/SW Co-Design

Custom instructions, tightly coupled accelerators, memory-mapped IP, DMA, embedded control, and software-visible neuromorphic hardware.

3. Physical AI & Event-Based Sensing

Intelligence operating in a real-time loop with the physical world.

Event-Based Vision

Event cameras, optical flow, sparse temporal processing, SNN perception, and low-latency FPGA acceleration.

Near-Sensor Intelligence

Processing close to sensors to reduce bandwidth, latency, memory traffic, and energy.

Robotics & Autonomous Systems

Embedded intelligence, sensing, control, adaptive hardware, and real-time decision-making for physical systems.

4. Emerging & Bio-Inspired Circuits

Alternative devices, circuits, and dynamical systems for future intelligent hardware.

Mixed-Signal Neuromorphic Circuits

Analog/digital neuron and synapse circuits, event interfaces, nonlinear dynamics, robustness, and circuit-level efficiency.

Memristive & In-Memory Computing

Emerging devices, compact models, device non-idealities, synaptic behavior, and memory-centric computing.

Bio-Inspired Dynamics

Central pattern generators, oscillators, coupled systems, biologically plausible models, and hardware realizations.

5. Hardware Security & Trust

Trustworthy architectures for increasingly autonomous computing systems.

Hardware Roots of Trust

Secure boot, device identity, PUFs, cryptographic hardware, lifecycle controls, and attestation.

Runtime Trust Monitoring

Hardware-level observation, anomaly detection, independent monitoring, and resilient platform architectures.

Trustworthy AI Hardware

Verification, fault resilience, secure accelerators, adversarial robustness, and assurance for intelligent embedded systems.

See the research in practice

Our Projects page connects these research themes to specific platforms, datasets, prototypes, publications, and student work.

Explore ProjectsView Publications

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