SHaRe Lab

Research & Projects

SHaRe develops specialized hardware from algorithm to silicon. Our work spans Physical AI and event-based sensing, machine-learning acceleration, AI-assisted design automation, neuromorphic computing, digital signal processing, communication hardware, and hardware trust. Across these areas, we co-design algorithms and architectures rather than treating hardware implementation as an afterthought.

01 / Physical AI

Physical AI and Event-Based Sensing

Intelligent hardware that senses, computes, and acts under the real-time latency, bandwidth, and power constraints of physical systems.

  • Event-based vision. FPGA and SNN processing for dynamic-vision sensors, including optical flow, feature extraction, and spiking Hough-transform architectures.
  • Near-sensor intelligence. Moving computation closer to sensors to reduce data movement and enable low-latency autonomous operation.
  • Physical test platforms. Micro-drone and embedded platforms for evaluating custom sensing and acceleration hardware under realistic operating conditions.
Selected reading:
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02 / AI Hardware

Machine Learning and AI Accelerators

Specialized architectures that map modern machine-learning workloads efficiently onto FPGA and ASIC hardware.

  • Neural-network accelerators. Custom datapaths, memory hierarchies, parallelism, sparsity, quantization, and dataflow optimization for efficient inference.
  • Transformer acceleration. Streaming, low-precision, LUT-centric, and multiplier-reduced architectures with hardware-aware attention and memory organization.
  • Algorithm鈥揾ardware co-design. Adapting model structure, precision, and computational effort to the capabilities and constraints of the target hardware.
Selected reading:
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03 / AI for Design

AI-Assisted Design and Optimization

Using AI and large language models to accelerate the path from algorithmic intent to verified and optimized hardware.

  • Algorithm-to-architecture translation. AI-assisted exploration of hardware mappings, datapaths, partitioning, and implementation trade-offs.
  • RTL generation and refinement. Generating, reviewing, and improving synthesizable Verilog/SystemVerilog from specifications and higher-level models.
  • Verification and debugging. AI-guided test generation, failure analysis, bug localization, and iterative hypothesis-driven verification.
  • Design-space exploration. Combining AI agents with synthesis and implementation tools to optimize area, timing, power, and functionality.
Selected reading:
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04 / Neuromorphic

Neuromorphic and Bio-Inspired Computing

Brain-inspired models and architectures studied as one part of our broader specialized-hardware research program.

  • Neural Assembly Computing. Assembly-level computation, state-space formulations, planning, and new representations for scalable neuromorphic systems.
  • Hardware-efficient neuron and synapse models. Izhikevich, Rulkov, chaotic map-based neurons, learning rules, and mixed digital/analog implementations.
  • Memristive and emerging-device computing. Memristor models, synaptic circuits, associative learning, in-memory computation, and device-aware neuromorphic architectures.
  • Neuromorphic platforms. Modular NPUs and scalable multi-FPGA architectures for large spiking neural networks and real-time embedded intelligence.
Selected reading:
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05 / DSP

DSP and Communication Hardware

Hardware architectures for signal processing and communication systems, with emphasis on precision, throughput, latency, and implementation efficiency.

  • Fixed-point DSP architectures. Word-length optimization, numerical error analysis, custom arithmetic, pipelining, and hardware-aware signal-processing implementation.
  • Spectral and temporal processing. Hardware-oriented filtering, transforms, feature extraction, and efficient processing of time-series and sensor data.
  • Communication hardware. Digital processing and front-end architectures for high-speed links, optical communication, coding, and signal-conditioning systems.
Selected reading:
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06 / Trust

Hardware Security and Trusted Systems

Security and trust mechanisms rooted in circuit behaviour, device variability, nonlinear dynamics, and hardware-level observation.

  • Physical unclonable functions. Analog, delay-based, bistable, and spiking-neuron PUFs with circuit- and dynamical-system-level modelling.
  • Entropy and lightweight cryptography. Chaotic random-number generation and compact cryptographic architectures for constrained embedded devices.
  • Trusted intelligent systems. IC authentication, hardware-rooted monitoring, resilient architectures, and trust management for autonomous platforms.
Selected reading:
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Open Research Outputs

Selected datasets and software released alongside our research.

Dataset

Event-based human-motion optical-flow dataset supporting our event-based vision research.
Software
symnoise
Open-source Python implementation of Symbolic Noise Analysis for hardware precision optimization.

Explore our publications

The links above highlight representative work. The complete publication record spans hardware optimization, DSP, AI acceleration, neuromorphic computing, mixed-signal circuits, and hardware security.

SHaRe Publications

Interested in working with us?

Prospective students should identify one or two areas that match their background and explain the problem, algorithm,
or hardware system they would like to investigate or build.

Join SHaRe

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