Abstract: Neuromorphic computing has emerged as an event-driven, energy-efficient paradigm for brain-like information processing. Unlike conventional architectures, it unifies memory and computation to mitigate the von Neumann bottleneck, and it typically relies on spiking neural networks (SNNs) as its computational model. As SNNs grow in structure and scale, their hardware acceleration becomes increasingly important for performance and power efficiency. Among the available platforms, graphics processing units (GPUs) and the open-standard RISC-V instruction set occupy a distinctive position: both remain fully software-programmable, yet they sit at opposite ends of the throughput-versus-efficiency spectrum, which makes their joint study particularly informative for neuromorphic system design. This survey reviews 71 studies published between 2015 and 2025 (45 GPU-based and 26 RISC-V-based) and organizes them into a taxonomy that classifies GPU works into simulation frameworks, training-acceleration techniques, large-scale and multi-GPU simulation, and application deployments, and RISC-V works into instruction-set extensions and tightly-coupled cores, accelerator system-on-chips, programmable neuromorphic processors, and edge deployments. For each study, we extract the software frameworks, learning methods, SNN architectural features, network scale, power and energy, speedup, memory use, runtime, and throughput, and we consolidate the comparable metrics to expose the order-of-magnitude separation between the two platforms in operating power and supported network size. A coverage analysis of the corpus shows that the two communities report largely disjoint metric sets (GPU studies emphasize runtime and speedup, RISC-V studies emphasize power and latency), which we identify as the structural reason a fair head-to-head comparison is currently infeasible; and we note that the efficiency advantage of dedicated neuromorphic chips, used here as the baseline, stems substantially from near- and in-memory organization that itself carries area and energy costs. Building on the gaps identified across the corpus, the survey outlines research directions for next-generation GPU and RISC-V accelerators, including heterogeneous workload partitioning, standardized benchmarking, and integration with emerging in-memory technologies.

Contest Highlights:

• $10,000 prize pool and free development kits
• Hands-on experience with Microchip PolarFire® FPGA platforms
• Open to students, working professionals, and FPGA enthusiasts
• Opportunity to develop and showcase innovative FPGA-based solutions
• Participate in teams of 2–3 members
• Showcase your work on a global stage

We would greatly appreciate your support in sharing this opportunity with interested students, faculty colleagues, FPGA clubs, and academic networks.

Contest Information
Contest Page:
LinkedIn Post:

Refer to these links for information on our FPGA development platforms, documentation, example demos, getting started guides, knowledge articles etc.

Please find the attached slide deck and flyer, which you may use to promote the contest within your student and academic communities.

For any questions or additional information, please contact fpgacontesthelp@microchip.com

Abstract: This thesis presents EmFlow, a hardware-oriented spiking neural network (SNN) for high-speed embedded event-based optical flow estimation. EmFlow uses sparse convolutional processing, delayed upscaling, 1-bit spike feature maps, and limited persistent membrane state to reduce memory and computation. It is evaluated on HFlow320, a synthetic event-based human-motion dataset developed for this work, as well as MVSEC evaluation sequences and the DSEC optical-flow benchmark. With the baseline 25 ms hardware-oriented input window, EmFlow achieves 2.39 px endpoint error (EPE) and 35.02â—¦ average angular error (AAE) on HFlow320, 1.77 px EPE and 28.01â—¦ AAE on MVSEC, and 9.43 px EPE and 28.13â—¦ AAE on DSEC. The design is implemented on an AMD Kria KV260 field-programmable gate array (FPGA) with a Prophesee GenX320 event camera. The EmFlow accelerator module uses 9.6k look-up tables (LUTs), 11.8k flip-flops (FFs), 16 digital signal processing (DSP) blocks, 20/1 block RAM (BRAM) 36K/18K tiles, and 12 UltraRAM (URAM) tiles while sustaining a 40 frames/s (FPS) displayed output rate in live demonstrations. Event-to-observed-flow response measurements range from approximately 1.7 to 7 ms, while final displayed flow frames are accumulated over five 5 ms event windows. During operation, the system consumes 3.7 to 4.0 W total measured system-on-module (SOM) power, corresponding to approximately 0.1 to 0.4 W above the loaded idle baseline.

Abstract: Spiking neural networks (SNNs) are increasingly valued for their ability to emulate the temporal dynamics of biological neurons within hardware-efficient architectures. However, commonly used neuron models, such as Integrate-and-Fire (IF) and Leaky Integrate-and-Fire (LIF), fall short in capturing the complex chaotic spiking-bursting behaviors found in biological neurons, which can accelerate learning and improve accuracy. To address these limitations, we introduce an optimized two-dimensional map-based neuron model (called the MR model), adapted from the Rulkov model, that efficiently achieves chaotic spiking-bursting behavior while minimizing computational demands. This model overcomes typical trade-offs between accuracy and efficiency, making it suitable for digital implementation in both hardware and software contexts. As a proof of concept, an FPGA-based implementation demonstrates the model’s resource efficiency. In image classification tasks, incorporating chaotic dynamics in only 1% of neurons resulted in up to 20% higher accuracy and a 50% reduction in convergence time compared to standard neuron models. These findings indicate that chaotic dynamics in SNNs can significantly enhance learning performance, providing an effective approach for real-time neuromorphic applications.

keywords: Modeling; Neurons; Dynamics; Hardware; Accuracy; Learning (artificial intelligence); Costing; Costs; Limit-cycles; Spiking neural networks; Pattern recognition; map-based neuron models; dynamic systems; spiking-bursting; chaotic regime; neuromorphic; FPGA; Spiking Neural Network (SNN),

Build innovative AI applications accelerated by AMD Radeon™ GPUs and the ROCm™ software stack and compete for a share of the $30,000 USD prize pool.

Good luck!

SHaRe Team

The SHaRe Lab is pleased to host Aliza Ghani on the Universal Verification Methodology (UVM) and its application to Spiking Neural Network Design.

Aliza will introduce UVM (IEEE 1800.2) as a framework for verifying complex digital designs, walking through the verification challenges that motivate it, its component-based testbench architecture, and the constrained-random, coverage-driven approach that makes it the industry standard. She will then connect the methodology to neuromorphic hardware, showing how UVM maps naturally onto the layered structure of spiking neural networks (SNNs), with a worked example built around a Leaky Integrate-and-Fire (LIF) neuron testbench. The talk closes with a concrete SystemVerilog and UVM skeleton illustrating how each functional block of an SNN core can be verified independently.

The session is open to all lab members and the wider department. Graduate and undergraduate students with an interest in VLSI verification, FPGA design, and neuromorphic hardware are warmly encouraged to attend.

Speaker Bio

Aliza Ghani is an undergraduate Electrical Engineering student at NUST Islamabad. Her interests include hardware verification and digital design, with a focus on using UVM for functional verification, coverage analysis, and verification automation.

We are pleased to host Jin Shi, PhD candidate in Electrical and Electronic Engineering at the University of Nottingham, for a seminar on reliability-aware memristor crossbar computing and its applications in neuromorphic systems.

Abstract

This talk introduces recent work on reliability-aware memristor crossbar computing. Jin will discuss prior studies on wire resistance, sneak-path effects, and parasitic-aware modelling, followed by a preliminary study on mapping local SNN-Hough voting to analog crossbar current summation — a topic with direct relevance to hardware-efficient neuromorphic execution.

Speaker Bio

Jin Shi is a PhD candidate in Electrical and Electronic Engineering at the University of Nottingham. Her research focuses on memristor crossbar arrays for neuromorphic computing, spanning device non-idealities, parasitic-aware modelling, sneak-path analysis, and reliability-aware circuit- and system-level evaluation.

This will be an online informal and interactive session, all lab members are encouraged to attend and participate in the discussion.

Dr. Mohamad Moner Al Chawa with SHaRe Lab members, May 5, 2026 | 11:00 AM | Room ME4124, Mackenzie Building | ÐÓ°ÉÔ­´´ University

We were pleased to host for a seminar on compact modeling of memristive threshold switching devices and their applications in memory and neuromorphic circuits.

Dr. Al Chawa presented an efficient and physically motivated compact model for Ovonic Threshold Switching (OTS) devices, fabricated memristive components developed in collaboration with , whose experimentally measured current–voltage data was used to validate the model. The work addresses a key challenge in the field: bridging the gap between physically accurate device models and the computational efficiency required for practical circuit-level simulation. Using an internal state variable formulation, the model captures the off-state, snapback, and on-state device behavior, making it well-suited for neuromorphic and memory circuit design workflows.

The session drew strong engagement from faculty and students, with lively discussion on the implications of compact memristor modeling for neuromorphic hardware, closely aligned with the SHaRe Lab’s research in in-memory and memristive computing.

We thank Dr. Al Chawa for a stimulating and highly relevant talk and look forward to exploring future collaboration opportunities.

Abstract: Leveraging their inherent suitability for low power, parallel computation, Spiking Neural Networks (SNNs) are an emergent topic in energy-efficient image processing research. This paper investigates the use of SNNs for line detection using an algorithm inspired by the Hough Transform. The implementation targets a Zynq UltraScale+ MPSoC ZCU102 FPGA to compare utilization, power, latency, and accuracy results with CNN, CPU, and GPU implementations. Our approach of using a neural network replicates the voting scheme found in the conventional Hough Transform, but is 2.2 times faster and requires up to 86% less accumulator-equivalent memory compared to recently published, competing FPGA implementations. Furthermore, it uses up to 97% (86%) less estimated power than equivalent OpenCV implementations running on a CPU (GPU), albeit with diminished accuracy. To ensure scalability, we employ kernel transformation techniques, in which a single hardware kernel is used to scan the entirety of the input image. As a result, hardware utilization is independent of image size up to the configured maximum resolution. The reported design is capable of processing a 100 by 100 pixel image in 13 microseconds, while requiring only 6.7 KiB of on-chip algorithm state (accumulators, line-parameter lookup tables, and weights) for line clustering. This implementation demonstrates the potential of SNNs for use in efficient, hardware-accelerated image processing tasks.