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SHaRe develops specialized hardware from algorithm to silicon. Our work spans Physical AI and event-based sensing, machine-learning acceleration, AI-assisted design automation, neuromorphic computing, digital signal processing, communication hardware, and hardware trust. Across these areas, we co-design algorithms and architectures rather than treating hardware implementation as an afterthought.<\/p>\n<\/section>\n Intelligent hardware that senses, computes, and acts under the real-time latency, bandwidth, and power constraints of physical systems.<\/p>\n Specialized architectures that map modern machine-learning workloads efficiently onto FPGA and ASIC hardware.<\/p>\n Using AI and large language models to accelerate the path from algorithmic intent to verified and optimized hardware.<\/p>\n Brain-inspired models and architectures studied as one part of our broader specialized-hardware research program.<\/p>\n Hardware architectures for signal processing and communication systems, with emphasis on precision, throughput, latency, and implementation efficiency.<\/p>\n Security and trust mechanisms rooted in circuit behaviour, device variability, nonlinear dynamics, and hardware-level observation.<\/p>\n Selected datasets and software released alongside our research.<\/p>\n HFlow320<\/a><\/p>\n The links above highlight representative work. The complete publication record spans hardware optimization, DSP, AI acceleration, neuromorphic computing, mixed-signal circuits, and hardware security.<\/p>\n Google Scholar<\/a>SHaRe Publications<\/a><\/p>\n<\/section>\n Prospective students should identify one or two areas that match their background and explain the problem, algorithm,Physical AI and Event-Based Sensing<\/h2>\n
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\nSpiking Hough Transform on FPGA<\/a>\u2022<\/span>Event-Based Vision: A Survey<\/a>\u2022<\/span>HFlow320 Dataset<\/a><\/div>\n<\/div>\nMachine Learning and AI Accelerators<\/h2>\n
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\nRobust Recognition with Transformer-Based Attention<\/a>\u2022<\/span>Eyeriss: Energy-Efficient CNN Acceleration<\/a>\u2022<\/span>TPU Architecture<\/a><\/div>\n<\/div>\n<\/div>\nAI-Assisted Design and Optimization<\/h2>\n
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\nRTLLM: RTL Generation with Large Language Models<\/a>\u2022<\/span>AlphaChip \/ RL for Chip Placement<\/a>\u2022<\/span>Related SHaRe Publications<\/a><\/div>\n<\/div>\nNeuromorphic and Bio-Inspired Computing<\/h2>\n
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\nCost-Efficient Chaotic Neuron for SNN Learning<\/a>\u2022<\/span>FPGA Neuromorphic Computing Survey<\/a>\u2022<\/span>Digital Hardware Neuron Models<\/a>\u2022<\/span>Memristor-Based Associative Learning<\/a>\u2022<\/span>Compact Memristor Model<\/a><\/div>\n<\/div>\n<\/div>\nDSP and Communication Hardware<\/h2>\n
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\nWord-Length Multiobjective Optimization<\/a>\u2022<\/span>Symbolic Noise Analysis for Hardware Optimization<\/a>\u2022<\/span>Related SHaRe Publications<\/a><\/div>\n<\/div>\nHardware Security and Trusted Systems<\/h2>\n
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\nBistable PUF Analysis and Dynamical Model<\/a>\u2022<\/span>SIMON Hardware Implementation<\/a>\u2022<\/span>Related SHaRe Publications<\/a><\/div>\n<\/div>\n<\/div>\n<\/section>\nOpen Research Outputs<\/h2>\n
Explore our publications<\/h2>\n
Interested in working with us?<\/h2>\n
\nor hardware system they would like to investigate or build.<\/p>\n