  {"id":30,"date":"2024-07-08T11:28:23","date_gmt":"2024-07-08T15:28:23","guid":{"rendered":"https:\/\/carleton.ca\/share\/?page_id=30"},"modified":"2026-08-27T18:34:04","modified_gmt":"2026-08-27T22:34:04","slug":"research","status":"publish","type":"page","link":"https:\/\/carleton.ca\/share\/research\/","title":{"rendered":"Research"},"content":{"rendered":"<div style=\"max-width: 1120px; margin: 0 auto; font-family: Arial,Helvetica,sans-serif; color: #222222; line-height: 1.65;\">\n<section style=\"padding: 38px 32px; margin: 0 0 30px 0; background: #F6F6F6; border-top: 5px solid #C8102E; border-radius: 0 0 10px 10px;\">\n<div style=\"font-size: 13px; font-weight: bold; letter-spacing: 1.5px; text-transform: uppercase; color: #c8102e; margin-bottom: 8px;\">SHaRe Lab<\/div>\n<h1 style=\"font-size: 38px; line-height: 1.16; margin: 0 0 14px 0; color: #222222;\">Research<\/h1>\n<p style=\"font-size: 18px; line-height: 1.7; margin: 0; max-width: 930px; color: #606060;\">We develop models, architectures, and hardware systems for neuromorphic computing, intelligent hardware, Physical AI, emerging circuits, and hardware trust.<\/p>\n<\/section>\n<section style=\"margin: 0 0 42px 0;\">\n<h2 style=\"font-size: 29px; margin: 0 0 10px 0; color: #222222; border-left: 5px solid #C8102E; padding-left: 12px;\">Our Research Framework<\/h2>\n<p style=\"font-size: 17px; color: #606060; margin: 0 0 18px 0;\">SHaRe connects three levels of research rather than treating algorithms and hardware as separate activities.<\/p>\n<div style=\"display: grid; grid-template-columns: repeat(auto-fit,minmax(250px,1fr)); gap: 15px;\">\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<div style=\"font-size: 12px; font-weight: bold; letter-spacing: 1px; text-transform: uppercase; color: #c8102e; margin-bottom: 7px;\">1<\/div>\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Models &amp; Algorithms<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Neuron models, SNNs, learning, signal processing, event representations, bio-inspired dynamics, and hardware-aware computation.<\/div>\n<\/div>\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<div style=\"font-size: 12px; font-weight: bold; letter-spacing: 1px; text-transform: uppercase; color: #c8102e; margin-bottom: 7px;\">2<\/div>\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Architectures &amp; Hardware<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">FPGA, ASIC, RISC-V, embedded, mixed-signal, memristive, and memory-centric architectures.<\/div>\n<\/div>\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<div style=\"font-size: 12px; font-weight: bold; letter-spacing: 1px; text-transform: uppercase; color: #c8102e; margin-bottom: 7px;\">3<\/div>\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Physical Systems<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Event-driven sensing, robotics, biomedical signals, communications, autonomous platforms, and near-sensor intelligence.<\/div>\n<\/div>\n<\/div>\n<div style=\"margin-top: 18px; padding: 19px 21px; background: #FFF8F0; border-left: 4px solid #C8102E;\"><strong>Core philosophy:<\/strong> a research idea is most valuable when we understand both its computational behavior and the cost of realizing it in hardware.<\/div>\n<\/section>\n<section style=\"margin: 0 0 44px 0;\">\n<h2 style=\"font-size: 29px; margin: 0 0 10px 0; color: #222222; border-left: 5px solid #C8102E; padding-left: 12px;\">1. Neuromorphic Computing<\/h2>\n<p style=\"font-size: 17px; color: #606060; margin: 0 0 18px 0;\">Brain-inspired computation from neuron dynamics to scalable architectures.<\/p>\n<div style=\"display: grid; grid-template-columns: repeat(auto-fit,minmax(255px,1fr)); gap: 14px;\">\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Spiking Neural Networks<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Architectures, learning, coding, recurrent networks, temporal processing, and hardware-efficient SNN models.<\/div>\n<\/div>\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Neuron &amp; Synapse Models<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">LIF, Izhikevich, AdEx, Hodgkin\u2013Huxley, resonate-and-fire, map-based neurons, nonlinear dynamics, and plastic synapses.<\/div>\n<\/div>\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Neuromorphic Architectures<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Scalable event-driven compute fabrics, routing, memory organization, heterogeneous accelerators, and distributed systems.<\/div>\n<\/div>\n<\/div>\n<\/section>\n<section style=\"margin: 0 0 44px 0;\">\n<h2 style=\"font-size: 29px; margin: 0 0 10px 0; color: #222222; border-left: 5px solid #C8102E; padding-left: 12px;\">2. Intelligent Hardware<\/h2>\n<p style=\"font-size: 17px; color: #606060; margin: 0 0 18px 0;\">Specialized architectures for efficient AI, signal processing, and domain-specific computation.<\/p>\n<div style=\"display: grid; grid-template-columns: repeat(auto-fit,minmax(255px,1fr)); gap: 14px;\">\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">FPGA &amp; RTL<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Pipelining, parallel datapaths, fixed-point arithmetic, memory hierarchy, high-speed interfaces, verification, and hardware-aware optimization.<\/div>\n<\/div>\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">ASIC &amp; AI-on-a-Chip<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Custom digital architectures, low-power data movement, specialized arithmetic, on-chip memory, accelerator integration, and silicon implementation.<\/div>\n<\/div>\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">RISC-V &amp; HW\/SW Co-Design<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Custom instructions, tightly coupled accelerators, memory-mapped IP, DMA, embedded control, and software-visible neuromorphic hardware.<\/div>\n<\/div>\n<\/div>\n<\/section>\n<section style=\"margin: 0 0 44px 0;\">\n<h2 style=\"font-size: 29px; margin: 0 0 10px 0; color: #222222; border-left: 5px solid #C8102E; padding-left: 12px;\">3. Physical AI &amp; Event-Based Sensing<\/h2>\n<p style=\"font-size: 17px; color: #606060; margin: 0 0 18px 0;\">Intelligence operating in a real-time loop with the physical world.<\/p>\n<div style=\"display: grid; grid-template-columns: repeat(auto-fit,minmax(255px,1fr)); gap: 14px;\">\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Event-Based Vision<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Event cameras, optical flow, sparse temporal processing, SNN perception, and low-latency FPGA acceleration.<\/div>\n<\/div>\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Near-Sensor Intelligence<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Processing close to sensors to reduce bandwidth, latency, memory traffic, and energy.<\/div>\n<\/div>\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Robotics &amp; Autonomous Systems<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Embedded intelligence, sensing, control, adaptive hardware, and real-time decision-making for physical systems.<\/div>\n<\/div>\n<\/div>\n<\/section>\n<section style=\"margin: 0 0 44px 0;\">\n<h2 style=\"font-size: 29px; margin: 0 0 10px 0; color: #222222; border-left: 5px solid #C8102E; padding-left: 12px;\">4. Emerging &amp; Bio-Inspired Circuits<\/h2>\n<p style=\"font-size: 17px; color: #606060; margin: 0 0 18px 0;\">Alternative devices, circuits, and dynamical systems for future intelligent hardware.<\/p>\n<div style=\"display: grid; grid-template-columns: repeat(auto-fit,minmax(255px,1fr)); gap: 14px;\">\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Mixed-Signal Neuromorphic Circuits<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Analog\/digital neuron and synapse circuits, event interfaces, nonlinear dynamics, robustness, and circuit-level efficiency.<\/div>\n<\/div>\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Memristive &amp; In-Memory Computing<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Emerging devices, compact models, device non-idealities, synaptic behavior, and memory-centric computing.<\/div>\n<\/div>\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Bio-Inspired Dynamics<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Central pattern generators, oscillators, coupled systems, biologically plausible models, and hardware realizations.<\/div>\n<\/div>\n<\/div>\n<\/section>\n<section style=\"margin: 0 0 44px 0;\">\n<h2 style=\"font-size: 29px; margin: 0 0 10px 0; color: #222222; border-left: 5px solid #C8102E; padding-left: 12px;\">5. Hardware Security &amp; Trust<\/h2>\n<p style=\"font-size: 17px; color: #606060; margin: 0 0 18px 0;\">Trustworthy architectures for increasingly autonomous computing systems.<\/p>\n<div style=\"display: grid; grid-template-columns: repeat(auto-fit,minmax(255px,1fr)); gap: 14px;\">\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Hardware Roots of Trust<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Secure boot, device identity, PUFs, cryptographic hardware, lifecycle controls, and attestation.<\/div>\n<\/div>\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Runtime Trust Monitoring<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Hardware-level observation, anomaly detection, independent monitoring, and resilient platform architectures.<\/div>\n<\/div>\n<div style=\"padding: 21px; border: 1px solid #E1E1E1; border-radius: 8px; background: #fff;\">\n<h3 style=\"margin: 0 0 8px 0; font-size: 21px; line-height: 1.3; color: #222222;\">Trustworthy AI Hardware<\/h3>\n<div style=\"font-size: 16px; color: #414141; line-height: 1.65;\">Verification, fault resilience, secure accelerators, adversarial robustness, and assurance for intelligent embedded systems.<\/div>\n<\/div>\n<\/div>\n<\/section>\n<section style=\"padding: 28px; margin: 0 0 24px 0; background: #2C2C2C; color: #fff; border-radius: 8px;\">\n<h2 style=\"font-size: 28px; margin: 0 0 10px 0; color: white;\">See the research in practice<\/h2>\n<p style=\"margin: 0 0 14px 0; color: #eee;\">Our Projects page connects these research themes to specific platforms, datasets, prototypes, publications, and student work.<\/p>\n<p><a style=\"display: inline-block; padding: 11px 17px; margin: 4px 8px 4px 0; background: #C8102E; color: #fff; text-decoration: none; border: 1px solid #C8102E; border-radius: 5px; font-weight: bold;\" href=\"https:\/\/carleton.ca\/share\/projects\/\">Explore Projects<\/a><a style=\"display: inline-block; padding: 11px 17px; margin: 4px 8px 4px 0; background: #fff; color: #222222; text-decoration: none; border: 1px solid #D7D7D7; border-radius: 5px; font-weight: bold;\" href=\"https:\/\/carleton.ca\/share\/publications\/\">View Publications<\/a><\/p>\n<\/section>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>SHaRe Lab Research We develop models, architectures, and hardware systems for neuromorphic computing, intelligent hardware, Physical AI, emerging circuits, and hardware trust. Our Research Framework SHaRe connects three levels of research rather than treating algorithms and hardware as separate activities. 1 Models &amp; Algorithms Neuron models, SNNs, learning, signal processing, event representations, bio-inspired dynamics, and [&hellip;]<\/p>\n","protected":false},"author":5,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_relevanssi_hide_post":"","_relevanssi_hide_content":"","_relevanssi_pin_for_all":"","_relevanssi_pin_keywords":"","_relevanssi_unpin_keywords":"","_relevanssi_related_keywords":"","_relevanssi_related_include_ids":"","_relevanssi_related_exclude_ids":"","_relevanssi_related_no_append":"","_relevanssi_related_not_related":"","_relevanssi_related_posts":"","_relevanssi_noindex_reason":"","_mi_skip_tracking":false,"_exactmetrics_sitenote_active":false,"_exactmetrics_sitenote_note":"","_exactmetrics_sitenote_category":0,"footnotes":"","_links_to":"","_links_to_target":""},"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v21.2 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Research Areas | SHaRe Lab, 杏吧原创 University<\/title>\n<meta name=\"description\" content=\"Research areas at SHaRe Lab: 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