News Archives - Specific-domain Hardware Research Laboratory

Industry Talk: Advanced FPGA Design Practices

Arash Ahmadi — Tue, 14 Apr 2026 19:37:10 +0000

Industry Talk: Advanced FPGA Design Practices with Fidus Systems

April 22, 2026 | 4:30 PM – 6:00 PM | Nicol Building, Room 5010 (NI 5010)

We are pleased to host , a senior FPGA engineer at ,

This technical talk draws from a curated set of advanced FPGA design topics reflecting real-world industry practices at one of Canada’s leading FPGA design services companies. Topics to be covered include FSM RTL design, FPGA simulation automation and best practices, SystemRDL for register design, Clock Domain Crossing (CDC), High-Level Synthesis (HLS), and typical SoC FPGA project structure and scripting workflows.

Dessislav is no stranger to our community — he joined us earlier in the term for the series’ opening drop-in session in February, where he engaged directly with students on their projects and research. This session marks his return in a more formal speaking capacity and brings the series to a strong technical close.

This event is the fifth of a Winter 2026 collaboration with , which has brought experienced engineers from industry to campus across a series of drop-in sessions and seminars. The series has engaged students from Depertment of Electronics resulting in mentorship opportunities, project feedback, and graduate student internship referrals.

Industry Engagement: Drop-In Session with Fidus Microsystems

Arash Ahmadi — Thu, 26 Mar 2026 11:53:52 +0000

Drop-in session with Fidus Microsystems engineers Victor Dumitriu and Matt Fransham | ME 4166, March 25, 2026.

It was a great pleased to host and from for the second drop-in session of our Winter 2026 industry engagement series.

The session brought together students for an open, informal discussion with two experienced FPGA engineers. Students had the opportunity to present their ongoing projects and receive direct feedback, while Victor and Matt shared their professional insights on industry workflows, design standards, and what it means to work at a high-caliber FPGA design services company.

The conversation was candid, energetic, and highly valued by all who attended — a testament to the kind of meaningful exchange that bridges the gap between academic research and professional engineering practice.

We extend our sincere thanks to Victor Dumitriu, Matt Fransham, and the entire Fidus Microsystems team for their continued generosity and commitment to supporting the next generation of FPGA engineers at �Ӱ�ԭ��.

This session is part of an ongoing collaboration with Fidus Microsystems, bringing industry professionals to campus to engage directly with our team throughout the 2026 winter term. More sessions are planned — stay tuned!

Network with Industry Professionals – Fidus Drop-In Session | Mar 25

Arash Ahmadi — Wed, 18 Mar 2026 16:01:16 +0000

March 11th, we are hosting Fidus Microsystems at DoE FPGA/SoC Dropping Centre.

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Date: Wednesday, March 25, 2026
Time: 4:30 PM – 6:00 PM
Location: Mackenzie Building, Room 4166 (ME 4166)
Guests: Victor Dumitru & Matt Frasham (Fidus Microsystems)
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Drop-in sessions are informal and conversational — come as you are and bring your questions. This is also a great opportunity to showcase your projects and skills to working engineers. As we have seen with previous sessions, these conversations can naturally evolve into something more, including internship and co-op opportunities.

We look forward to seeing you there!

Industry Talk Recap: Bridging the Gap Between Student and Industry Professional

Arash Ahmadi — Thu, 12 Mar 2026 15:22:29 +0000

Christian Kamps (Fidus Microsystems) with students following the talk, March 11, 2026.

March 11, 2026 | 4:30 PM – 6:00 PM | ME 3328, Mackenzie Building

We were pleased to host , a Department of Electronics alumnus and FPGA Designer at , for an engaging industry talk tailored to students considering careers in digital hardware design.

Drawing directly on his own transition from �Ӱ�ԭ�� to a professional engineering role, Christian walked through what it actually means to work as a junior FPGA designer — from day-to-day responsibilities and tool workflows to the gap between academic projects and real industry expectations. He addressed common misconceptions about FPGA careers and offered candid, practical advice for students preparing to make that same transition.

This session was part of an ongoing series of industry engagements with , bringing working engineers into our courses to share experience and connect with students directly.

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Next Session: Drop-In with Victor Dumitru & Matt Frasham
March 25, 2026 | 4:30 – 6:00 PM | ME 4166
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The drop-in format is informal — bring your questions, your projects, and your curiosity. More details to follow.

New Publication

Arash Ahmadi — Fri, 06 Mar 2026 15:53:23 +0000

Abstract: We propose the analysis and dynamical system model for one-dimensional bistable Physically Unclonable Function (PUF). Our work is derived from the analysis of a broad range of analytical models and circuit topologies suitable for the design of bistable PUFs. Starting from circuit analysis, we discuss a theoretical model to evaluate the source of entropy from a mathematical point of view targeting optimized intrinsic hardware-based security mechanisms. The results develop an evaluation design tool to address the most crucial model parameters affecting the obtained system uniqueness. The analysis is authentic as it is generalized by a systematic standpoint framing the PUF design within a mathematical context. The paper presents a methodical approach aiming at defining a novel class of beneficial models exploiting the dynamics sensitivity to parametric perturbations extending the PUF design within a theoretical setting. Furthermore, the proposed analysis is potentially investigated to explore the impacts of environmental conditions on system parametric perturbation affecting PUF reliability.

Bridging the Gap Between Engineering Student/Academic versus an Industry Professional

Arash Ahmadi — Tue, 03 Mar 2026 16:27:08 +0000

Industry Talk: The Role and Responsibilities of a Junior FPGA Designer

March 11, 2026 | 4:30 PM – 6:00 PM

Location: ME 3328 (Mackenzie)

We are pleased to host an industry session featuring , (�Ӱ�ԭ�� Alum) and Matt Carswell �ڰ��ǳ��.

Talk Title

“Bridging the Gap Between Engineering Student/Academic versus an Industry Professional”

This session explored the transition from student life to professional FPGA engineering. Christian discussed:

The role and responsibilities of a junior FPGA designer
Differences between academic project environments and industry workflows
Common misconceptions about FPGA careers
Practical advice for students preparing for industry roles

This session is particularly valuable for students considering careers in FPGA, embedded systems, and digital hardware design.

Industry Seminar: Memory Self-Repair

Arash Ahmadi — Fri, 27 Feb 2026 19:19:21 +0000

We host an industry seminar by , Principal Software Development Engineer at Siemens Digital Industries Software.

Luc will present “Introduction to Design-For-Test (DFT) and Memory Self-Repair”, offering an overview of modern structural test methodologies used in advanced SoC and ASIC development.

Date: Tuesday, March 3
Time: 7:00 PM – 8:30 PM
Location: ME (Mackenzie Building), Room 3235

�Ӱ�ԭ�� the Talk

As semiconductor systems continue to scale in complexity, Design-For-Test (DFT) has become a fundamental component of digital IC design. This seminar will introduce key concepts and industrial practices including:

Motivation and fundamentals of DFT
Scan insertion and Automatic Test Pattern Generation (ATPG)
IEEE 1149.1 (JTAG) and IJTAG (1687) standards
Logic BIST and Memory BIST architectures
Fault models and test coverage
Memory self-repair and redundancy techniques
Overview of Siemens Tessent silicon lifecycle solutions

�Ӱ�ԭ�� × Fidus Systems: FPGA Drop-In Session (Feb 25, 2026)

Arash Ahmadi — Wed, 18 Feb 2026 15:47:56 +0000

We are pleased to host the first Winter 2026 Fidus Systems FPGA Drop-In session, launching a new series of industry-supported student engagement events focused on practical FPGA and SoC design.

Fidus engineers—Dessislav Valkov and Arnold Balish—will be on campus to meet with students, answer questions, and discuss real-world design workflows, tools, and career paths in digital hardware and FPGA engineering.

Date: Wednesday, Feb 25, 2026
Time: 4:30 PM – 6:00 PM
Location: FPGA Drop-In Center, ME (Mackenzie) 4166
Format: Informal drop-in mentoring and discussion (no formal presentation)
Who should attend: Undergraduate and graduate students interested in FPGA, digital design, verification, and embedded systems

Students are welcome to bring questions related to coursework, projects, toolflows, design best practices, and industry expectations. This event marks the first of several Winter 2026 sessions as part of our growing collaboration with , aimed at bridging academic learning with industry practice.

New Publication

Arash Ahmadi — Wed, 18 Feb 2026 15:41:43 +0000

Robust face recognition under partial occlusions remains a key challenge in real-world biometric and surveillance systems. In this article, we propose a hybrid dual-branch model—channel-spatial faster vision transformer (CSFVIT)—that integrates local and global feature processing to enhance recognition performance under diverse occlusion scenarios. The local branch refines facial features using a parallel channel-spatial attention (PCSA) module based on ResNet-18, while the global branch leverages a faster vision Transformer (FasterViT) to capture long-range dependencies. A dynamic attention fusion (DAF) module adaptively balances these features based on occlusion severity. We validate our model on five benchmark datasets: CASIA-WebFace, LFW, Extended Yale B, ORL, and AR. The model achieves 97.46% accuracy on CASIA-WebFace, 97.62% on LFW, 99.39% on Extended Yale B, 98.78% on ORL, and 98.50% on AR (sunglasses)/97.50% (scarf), consistently outperforming state-of-the-art baselines. CSFVIT achieves consistently high recognition accuracy under both synthetic and real-world occlusions, outperforming several attention- and transformer-based baselines. This practical and efficient architecture demonstrates strong potential for real-world face recognition applications in unconstrained environments.

New Publication

Arash Ahmadi — Wed, 16 Apr 2025 16:38:47 +0000

Abstract: Neuromorphic computing represents hardware and software paradigms that emulate neural brain functionalities. Spiking neural networks (SNNs) are a promising brain-inspired computing approach to achieve power efficiency through event-driven processing using discrete asynchronous spikes, making them particularly effective for spatiotemporal data processing. The complex computational nature of SNNs requires intensive calculations and specialized algorithms to ensure accurate performance across different tasks. Hardware accelerators for neuromorphic computing, particularly for SNN implementations, have emerged primarily through field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). FPGAs are especially attractive for neuromorphic computing due to their flexibility, stability, programmability, reconfigurability, and rapid time to market. This research explores top-tier and well-known journal articles from the IEEE Xplore digital library and the Google Scholar databases including IEEE, ACM, Frontiers, Elsevier, Springer, MDPI, Wiley, arXiv, and Nature publishers. In this survey, various energy-efficient and high-performance FPGA implementations of spiking neurons and SNNs are reviewed. The accuracy rates of the implemented SNNs on different applications are investigated. Also, digital hardware optimization techniques for reconfigurable implementations are discussed. The synthesis results from the presented implementations are reported and compared in terms of cost (referring to utilized resources such as Registers/FFs, LUTs, Multipliers, DSP blocks, and Block RAMs), speed, and power/energy consumption. The survey concludes with recommendations for future research directions in FPGA-based neuromorphic computing.