Abstract: This thesis presents EmFlow, a hardware-oriented spiking neural network (SNN) for high-speed embedded event-based optical flow estimation. EmFlow uses sparse convolutional processing, delayed upscaling, 1-bit spike feature maps, and limited persistent membrane state to reduce memory and computation. It is evaluated on HFlow320, a synthetic event-based human-motion dataset developed for this work, as well as MVSEC evaluation sequences and the DSEC optical-flow benchmark. With the baseline 25 ms hardware-oriented input window, EmFlow achieves 2.39 px endpoint error (EPE) and 35.02â—¦ average angular error (AAE) on HFlow320, 1.77 px EPE and 28.01â—¦ AAE on MVSEC, and 9.43 px EPE and 28.13â—¦ AAE on DSEC. The design is implemented on an AMD Kria KV260 field-programmable gate array (FPGA) with a Prophesee GenX320 event camera. The EmFlow accelerator module uses 9.6k look-up tables (LUTs), 11.8k flip-flops (FFs), 16 digital signal processing (DSP) blocks, 20/1 block RAM (BRAM) 36K/18K tiles, and 12 UltraRAM (URAM) tiles while sustaining a 40 frames/s (FPS) displayed output rate in live demonstrations. Event-to-observed-flow response measurements range from approximately 1.7 to 7 ms, while final displayed flow frames are accumulated over five 5 ms event windows. During operation, the system consumes 3.7 to 4.0 W total measured system-on-module (SOM) power, corresponding to approximately 0.1 to 0.4 W above the loaded idle baseline.

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SHaRe Team

The SHaRe Lab is pleased to host Aliza Ghani on the Universal Verification Methodology (UVM) and its application to Spiking Neural Network Design.

Aliza will introduce UVM (IEEE 1800.2) as a framework for verifying complex digital designs, walking through the verification challenges that motivate it, its component-based testbench architecture, and the constrained-random, coverage-driven approach that makes it the industry standard. She will then connect the methodology to neuromorphic hardware, showing how UVM maps naturally onto the layered structure of spiking neural networks (SNNs), with a worked example built around a Leaky Integrate-and-Fire (LIF) neuron testbench. The talk closes with a concrete SystemVerilog and UVM skeleton illustrating how each functional block of an SNN core can be verified independently.

The session is open to all lab members and the wider department. Graduate and undergraduate students with an interest in VLSI verification, FPGA design, and neuromorphic hardware are warmly encouraged to attend.

Speaker Bio

Aliza Ghani is an undergraduate Electrical Engineering student at NUST Islamabad. Her interests include hardware verification and digital design, with a focus on using UVM for functional verification, coverage analysis, and verification automation.

We are pleased to host Jin Shi, PhD candidate in Electrical and Electronic Engineering at the University of Nottingham, for a seminar on reliability-aware memristor crossbar computing and its applications in neuromorphic systems.

Abstract

This talk introduces recent work on reliability-aware memristor crossbar computing. Jin will discuss prior studies on wire resistance, sneak-path effects, and parasitic-aware modelling, followed by a preliminary study on mapping local SNN-Hough voting to analog crossbar current summation — a topic with direct relevance to hardware-efficient neuromorphic execution.

Speaker Bio

Jin Shi is a PhD candidate in Electrical and Electronic Engineering at the University of Nottingham. Her research focuses on memristor crossbar arrays for neuromorphic computing, spanning device non-idealities, parasitic-aware modelling, sneak-path analysis, and reliability-aware circuit- and system-level evaluation.

This will be an online informal and interactive session, all lab members are encouraged to attend and participate in the discussion.

We are pleased to invite all faculty, students, and researchers to a seminar by from , Germany.

Threshold switching devices, such as Ovonic Threshold Switching (OTS) devices, are promising nonlinear nanoscale components for memory selectors, fast switching, and neuromorphic computing. However, accurate device models are often too complex for efficient circuit-level simulations.

This talk presents a compact modeling approach for threshold switching devices that combines circuit-level efficiency with a physically motivated description of the switching process. The model is developed starting from an LTspice macro-model, then extended through a mathematical description and a compact formulation based on an internal state variable. This internal state variable captures the delay associated with threshold switching and enables the model to reproduce the off-state, snapback region, and on-state behavior. The model is validated by fitting experimental current–voltage data from an OTS device manufactured by Western Digital Research.

The talk will also discuss how this type of compact model can support circuit simulations involving nonlinear devices for memory and neuromorphic hardware applications.

Speaker Bio

is a researcher in nanoscale device modeling and compact physics-based modeling of nonlinear electronic devices. His work focuses on memristive devices, including ReRAM and Ovonic Threshold Switching devices, as well as sensors and neuromorphic memristive systems. Dr. Al Chawa is connected to the broader memristive and neuromorphic research community through collaborations including with Professor Leon Chua.